A significant trend throughout IC development has been to reduce the size of the components of the IC's. As the size is reduced, the performance requirements of the materials of the components become more stringent. For CMOS devices (e.g. CMOS transistors) in particular, increased performance requirements have generally been met by aggressively scaling the thickness and/or dielectrical properties of the gate dielectric and the length of the channel of the transistors. As attempts have been made to scale down CMOS technology into the sub-0.1 micron dimensions, however, the performance requirements for the CMOS devices have proven so stringent that the technique of scaling either the gate dielectric or the channel length or both has been a very difficult and/or impractical solution for meeting the high performance requirements.
To meet the increased performance requirements of the smaller CMOS devices, it has been suggested to alter characteristics other than the gate dielectric and/or channel length of the devices. One such characteristic for which improvements have been suggested is the mobility of the carriers in the channel region. For example, strained-Silicon (“strained-Si” or “SSI”) may be incorporated into the channel region, since strained-Si is known to have greater carrier mobility characteristics than do the materials that have been more commonly used in the channel region of CMOS devices. (K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronsheim, M. leong, A. Grill, and H.-S. P. Wong, “Strained-Si NMOSFETs for High Performance CMOS Technology,” 2001 Symposium on VLSI Technology Digest of Technical Papers, 2001, p. 59.)
Formation of a strained-Si layer on a semiconductor wafer has been done in a variety of ways. One technique involves complex fabrication processes, which includes epitaxial growth steps, such as epitaxial growth of a relatively thick, graded silicon-germanium (SiGe) film 100 onto a silicon substrate 102 followed by epitaxial growth of a strained-Si layer 104 onto the SiGe film 100, as shown in FIGS. 1, 2 and 3. The strain in the strained-Si layer 104 is induced by the underlying SiGe film 100. The SiGe film 100 is typically formed with a graded concentration of Ge in the Si, wherein the concentration of the Ge is slowly increased as the SiGe film 100 is grown on the substrate 102. In order to produce high quality strained-Si it is essential to carefully control the stoichiometry of the layer during the SiGe epitaxial growth process. Thus, the introduction of the gases into the epitaxial growth reactor chamber (not shown) must be carefully varied during fabrication of the SiGe film 100. In this manner, the spacing between the atoms in the crystalline structure of the SiGe film 100 is slowly increased from the beginning 106 to the surface 108 of the SiGe film 100. When the Si layer 104 is epitaxially grown on top of the SiGe film 100 (FIG. 2), the increased spacing is effectively maintained between the Si atoms, which leads to a straining of the Si layer 104. A conventional CMOS transistor 110 (FIG. 3), having conventional source, drain and gate electrodes 112, 114 and 116 and a conventional gate oxide region 118, is then fabricated on top of the strained-Si layer 104. The increased spacing between the Si atoms in the strained-Si layer 104 enhances the mobility of the carriers in the channel region, which is formed in the strained-Si layer 104 under the gate oxide 118 and between the source and drain 112 and 114.
The epitaxial growth steps, particularly for the SiGe epitaxial growth procedure, increase the time and cost of fabrication required to form the IC. Thus, there is a tradeoff between the performance characteristics and the cost of the resulting IC. Additionally, the presence of the strained-Si layer 104 sets limitations on the temperatures at which any subsequent processing steps may be performed, thereby limiting the flexibility with which the subsequent processing steps may be performed. Furthermore, the relatively thick SiGe film 100 acts as a thermal insulation layer, so the CMOS transistors formed thereon are susceptible to self-heating during operation of the IC, thereby degrading the performance capability of the IC. Also, isolation of the CMOS transistor 110, typically with shallow trench isolation, must be defined in both the strained-Si layer 104 and the SiGe film 100 as well as in the silicon substrate 102, which adds to the complexity of the overall IC fabrication. Furthermore, this technique is prone to defects, which may occur in the SiGe film 100 and, thus, propagate into the strained-Si layer 104 and higher layers of materials. Such defects may involve threading dislocations in the crystalline structure of the various layers. The threading dislocations negatively impact carrier mobility, gate oxide quality and overall device performance.
It is with respect to these and other considerations that the present invention has evolved.